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www.semtech.com 1 power management SC411 synchronous buck pseudo-fixed frequency power supply controller june 2007 the SC411 is a constant on-time synchronous buck pwm controller in a space-saving mlpq package intended for use in notebook computers and other battery operated portable devices. features include high ef ciency and a fast dynamic response with no minimum on-time. the excellent transient response means that SC411 based solu- tions will require less output capacitance than competing xed frequency converters. the switching frequency is constant until a step-in load or line voltage occurs. during this time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. after the transient event, the controller frequency will return to steady-state operation. at light loads, powersave mode enables the SC411 to skip pwm pulses for better ef ciency. the output voltage can be adjusted from 0.5v to vcca. a frequency setting resistor sets the on-time for the controller. the integrated gate drivers feature adaptive shoot-through protection and soft-switching. additional features include cycle-by-cycle current limit, digital soft-start, over-voltage and under-voltage protection, a power good output and soft discharge upon shutdown. constant on-time for fast dynamic response programmable vout range = 0.5 ? vcca vbat range = 1.8v ? 25v dc current sense using low-side rds(on) sensing or sense resistor resistor programmable frequency cycle-by-cycle current limit digital soft-start powersave option over-voltage/under-voltage fault protection 10 a typical shutdown current low quiescent power dissipation power good indicator 1.2% reference integrated gate drivers with soft switching enable pin 16 pin mlpq (4mm x 4mm) output soft discharge upon shutdown notebook computers cpu/io supplies handheld terminals and pdas lcd monitors network power supplies description features typical application circuit applications c6 1uf r3 r6 vout c5 1nf r1 rton1 vbat pgood q1 c7 1uf r5 c1 0.1uf d1 c2 10uf vbat 5vsus l1 + c4 vout r2 10r r4 5vsus vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 q2 c3
2 ? 2007 semtech corp. www.semtech.com SC411 power management exceeding the speci cations below may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not implied. exposure to absolute maximum rated conditions for extended period s of time may affect device reliability. test conditions: v bat = 15v, en/psv = 5v, vcca = vddp = 5v, v out =1.25v, r ton = 1m . parameter conditions 25c -40c to 125c units min typ max min max input supplies vcca 5.0 4.5 5.5 v vddp 5.0 4.5 5.5 v vbat voltage off-time > 800ns 1.8 25 v vddp operating current fb > regulation point, i load = 0a 70 150 a vcca operating current fb > regulation point, i load = 0a 700 1100 a notes: 1) this device is esd sensitive. use of standard esd handling precautions is required. 2) calculated from package in still air, mounted to 3? to 4.5?, 4 layer fr4 pcb with thermal vias under the exposed pad per jes d51 standards. parameter symbol maximum units ton to vssa -0.3 to +25.0 v dh, bst to pgnd -0.3 to +30.0 v lx to pgnd -2.0 to +25.0 v pgnd to vssa -0.3 to +0.3 v bst to lx -0.3 to +6.0 v dl, ilim, vddp to pgnd - 0.3 to +6.0 v en/psv, fb, pgd, vcca, vout to vssa -0.3 to +6.0 v vcca to en/psv, fb, pgd, vout -0.3 to +6.0 v thermal resistance junction to ambient (2) (2) ja 31 c/w operating junction temperature range t j -40 to +125 c storage temperature range t stg -65 to +150 c ir re ow (soldering) 10s to 30s t pkg 260 c absolute maximum ratings (1) electrical characteristics
3 ? 2007 semtech corp. www.semtech.com SC411 power management parameter conditions 25c -40c to 125c units min typ max min max input supplies (cont.) ton operating current r ton = 1m 15 a shutdown current en/psv = 0v -5 -10 a vcca 5 10 a vddp, ton 0 1 a controller error comparator threshold (fb turn-on threshold) (1) vcca = 4.5v to 5.5v includes variations of internal x3 gain stage, com- parator, and 1.5v ref 0.500 -1.2% +1.2% v output voltage range 0.5 vcca v on-time, v bat = 2.5v r ton = 1m 1761 1409 2113 ns r ton = 500k 936 749 1123 minimum off-time 400 550 ns vout input resistance 500 k vout shutdown discharge resistance en/psv = gnd 22 fb input bias current -1.0 +1.0 a over-current sensing ilim source current dl high 10 9 11 a current comparator offset pgnd - ilim -10 10 mv psave zero-crossing threshold (pgnd - lx), en/psv = 5v 5mv fault protection electrical characteristics (cont.)
4 ? 2007 semtech corp. www.semtech.com SC411 power management parameter conditions 25c -40c to 125c units min typ max min max current limit (positive) (2) (pgnd - lx), r ilim = 5k 50 35 65 mv (pgnd - lx), r ilim = 10k 100 80 120 mv (pgnd - lx), r ilim = 20k 200 170 230 mv fault protection (cont.) current limit (negative) (pgnd - lx) -125 -160 -90 mv output under-voltage fault with respect to internal ref. -30 -40 -25 % output over-voltage fault with respect to internal ref. +16 +12 +20 % over-voltage fault delay fb forced above ov threshold 5 s pgd low output voltage sink 1ma 0.4 v pgd leakage current fb in regulation, pgd = 5v 1 a pgd uv threshold with respect to internal ref. -10 -12 -8 % pgd fault delay fb forced outside pgd window 5 s vcca under-voltage threshold falling (100mv hysteresis) 4.0 3.7 4.3 v over-temperature lockout 10c hysteresis 165 c inputs/outputs logic input low voltage en/psv low 1.2 v logic input high voltage en high, psv low (floating) 2.0 v logic input high voltage en/psv high 3.1 v en/psv input resistance r pullup to vcca 1.5 m r pulldown to vssa 1.0 electrical characteristics (cont.)
5 ? 2007 semtech corp. www.semtech.com SC411 power management notes: 1) when the inductor is in continuous and discontinuous conduction mode, the output voltage will have a dc regulation level hi gher than the error-comparator threshold by 50% of the ripple voltage. 2) using a current sense resistor, this measurement relates to pgnd minus the voltage of the source on the low-side mosfet. t hese values guaranteed by the ilim source current and current comparator offset tests. 3) clks = switching cycles. 4) guaranteed by design. see shoot-through delay timing diagram on page 8. 5) semtech?s smartdriver tm fet drive rst pulls dh high with a pull-up resistance of 10 (typ) until lx = 1.5v (typ). at this point, an additional pull-up device is activated, reducing the resistance to 2 (typ). this negates the need for an external gate or boost resistor. parameter conditions 25c -40c to 125c units min typ max min max soft-start soft-start ramp time en/psv high to pgd high 440 clks (3) under-voltage blank time en/psv high to uv high 440 clks (3) gate drivers shoot-through delay (4) dh or dl rising 30 ns dl pull-down resistance dl low 0.80 1.75 dl sink current dl = 2.5v 3.1 a dl pull-up resistance dl high 2 4 dl source current dl = 2.5v 1.3 a electrical characteristics (cont.)
6 ? 2007 semtech corp. www.semtech.com SC411 power management ov ton (16) monitor pwm + - toff en/psv (15) 1.5v ref vcca (2) ton isense bst (13) ref - 30% uv hi dh (12) lx (11) on lo ilim (10) off vddp (9) dl (8) zero pgnd (7) control logic por / ss vssa (6) fault ref + 16% oc ot pgd (4) x3 fb (3) ref - 10% vout (1) dschg dschg nc (5) nc (14) block diagram note: the error comparator tolerances are approximately x3 gain stage = +/- 0.1% gain error comparator = +/- 3mv offset error 1.5v ref = +/- 1.0% error comparator
7 ? 2007 semtech corp. www.semtech.com SC411 power management device package (1) SC411mltrt (2) mlpq-16 SC411evb evaluation board notes: 1) only available in tape and reel packaging. a reel contains 3000 devices. (2) lead free product. this product is fully weee, rohs and j-std-020b compliant. pin # pin name pin function 1 vout output voltage sense input. connect to the output at the load. 2 vcca supply voltage input for the analog supply. use a 10 /1 f rc lter from 5vsus to vssa. 3fb feedback input. connect to a resistor divider located at the ic from vout to vssa to set the output voltage from 0.5v to vcca. 4 pgd power good open drain nmos output. goes high after a xed clock cycle delay (440 cycles) following power up. 5 nc not connected. 6 vssa ground reference for analog circuitry. connect directly to thermal pad. 7 pgnd power ground. connect directly to thermal pad. 8 dl gate drive output for the low side mosfet switch. 9 vddp +5v supply voltage input for the gate drivers. decouple this pin with a 1 f ceramic capacitor to pgnd. 10 ilim current limit input. connect to drain of low-side mosfet for rds(on) sensing or the source for resistor sensing through a threshold sensing resistor. 11 lx phase node (junction of top and bottom mosfets and the output inductor) connection. top view 1 2 3 4 12 11 10 9 16 15 14 13 5678 mlpq16: 4x4 body t ton en/psv nc bst dh lx ilim vddp vout vcca fb pgd nc vssa pgnd dl pin con guration ordering information pin descriptions
8 ? 2007 semtech corp. www.semtech.com SC411 power management 12 dh gate drive output for the high side mosfet switch. 13 bst boost capacitor connection for the high side gate drive. 14 nc not connected. 15 en/psv enable/power save input. pull down to vssa to shut down vout and discharge it through 22 (nom.). pull up to enable vout and activate psave mode. float to enable vout ac- tivate continuous conduction mode (ccm). if oated, bypass to vssa with a 10nf ceramic capacitor. 16 ton this pin is used to sense vbat through a pullup resistor, rton, and to set the top mosfet on-time. bypass this pin with a 1nf ceramic capacitor to vssa. - thermal pad pad for heatsinking purposes. connect to ground plane using multiple vias. not connected internally. tplhdl tplhdh lx dl dl dh pin descriptions (cont.) shoot-through delay timing diagram
9 ? 2007 semtech corp. www.semtech.com SC411 power management +5v bias supplies the SC411 requires an external +5v bias supply in addi- tion to the battery. if stand-alone capability is required, the +5v supply can be generated with an external linear regulator such as the semtech lp2951. for optimal operation, the controller has its own ground reference, vssa, which should be tied along with pgnd directly to the thermal pad under the part, which in turn should connect to the ground plane using multiple vias. all external components referenced to vssa in the typical application circuit on page 1 located near their respec- tive pins. supply decoupling capacitors should be located adjacent to their respective pins. a 10 resistor should be used to decouple vcca from the main vddp supply. all ground connections are connected directly to the ground plane as mentioned above. vssa and pgnd should be starred at the thermal pad. the vddp input provides power to the upper and lower gate drivers; a decoupling capacitor is required. no series resistor between vddp and 5v is required. see layout guidelines on page 17 for more details. pseudo-fixed frequency constant on-time pwm controller the pwm control architecture consists of a constant on- time, pseudo xed frequency pwm controller (block dia- gram, page 6). the output ripple voltage developed across the output lter capacitor?s esr provides the pwm ramp signal eliminating the need for a current sense resistor. the high-side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. a second one-shot sets the minimum off-time which is typically 400ns. on-time one-shot (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a current. this input voltage-proportional current is used to charge an internal on-time capacitor. the on-time is the time re- quired for the voltage on this capacitor to charge from zero volts to vout, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. this implementation results in a nearly constant switching frequency without the need for a clock generator. for vout < 3.3v: ns 50 v v ) 10 x 37 r ( 10 x 3 . 3 t bat out 3 ton 12 on + ? ? ? ? ? ? ? ? ? + ? = ? for 3.3v vout 5v: r ton is a resistor connected from the input supply (vbat) to the ton pin. due to the high impedance of this resistor, the ton pin should always be bypassed to vssa using a 1nf ceramic capacitor. en/psv: enable, psave and soft discharge the en/psv pin enables the supply. when en/psv is tied to vcca the controller is enabled and power save will also be enabled. when the en/psv pin is tri-stated, an internal pull-up will activate the controller and power save will be disabled. if psave is enabled, the SC411 psave comparator will look for the inductor current to cross zero on eight consecutive switching cycles by comparing the phase node (lx) to pgnd. once observed, the controller will enter power save and turn off the low side mosfet when the current crosses zero. to improve light-load ef- ciency and add hysteresis, the on-time is increased by 50% in power save. the ef ciency improvement at light- loads more than offsets the disadvantage of slightly high- er output ripple. if the inductor current does not cross zero on any switching cycle, the controller will immediately exit power save. since the controller counts zero cross- ings, the converter can sink current as long as the cur- rent does not cross zero on eight consecutive cycles. this allows the output voltage to recover quickly in response to negative load steps even when psave is enabled. if the en/psv pin is pulled low, the related output will be shut down and discharged using a switch with a nominal resistance of 22 ohms. this will ensure that the output is in a de ned state next time it is enabled and also ensure, since this is a soft discharge, that there are no danger- ous negative voltage excursions to be concerned about. in order for the soft discharge circuitry to function correctly, the chip supply must be present. ns 50 v v ) 10 x 37 r ( 10 x 3 . 3 85 . 0 t bat out 3 ton 12 on + ? ? ? ? ? ? ? ? ? + ? ? = ? application information
10 ? 2007 semtech corp. www.semtech.com SC411 power management application information (cont.) output voltage selection the output voltage is set by the feedback resistors r3 & r5 of figure 2 below. the internal reference is 1.5v, so the voltage at the feedback pin is multiplied by three to match the 1.5v reference. therefore the output can be set to a minimum of 0.5v. the equation for setting the output voltage is: r3 v out = ( 1 + DDD ) ? 0.5 r5 figure 2: setting the output voltage current limit circuit current limiting of the SC411 can be accomplished in two ways. the on-state resistance of the low-side mosfet can be used as the current sensing element or sense resistors in series with the low-side source can be used if greater accuracy is desired. r ds(on) sensing is more ef- cient and less expensive. in both cases, the r ilim resis- tor between the ilim pin and lx pin sets the over current threshold. this resistor rilim is connected to a 10 a cur- rent source within the SC411 which is turned on when the low side mosfet turns on. when the voltage drop across the sense resistor or low side mosfet equals the voltage across the rilim resistor, positive current limit will activate. the high side mosfet will not be turned on until the voltage drop across the sense element (resistor or mosfet) falls below the voltage across the r ilim resis- tor. in an extreme over-current situation, the top mosfet will never turn back on and eventually the part will latch off due to output under-voltage (see output under-voltage protection). the current sensing circuit actually regulates the induc- tor valley current (see figure 3). this means that if the current limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus 1/2 the peak-to-peak ripple current. the equations for setting the valley current and calculating the average current through the inductor are shown below: figure 3: valley current limiting the equation for the current limit threshold is as follows: i limit = 10a r ilim / r sense (amps) where (referring to figure 4 on page 17) r ilim is r4 and r sense is the r ds(on) of q2. for resistor sensing, a sense resistor is placed between the source of q2 and pgnd. the current through the source sense resistor develops a voltage that opposes the voltage developed across r ilim . when the voltage devel- oped across the r sense resistor reaches the voltage drop across r ilim, a positive over-current exists and the high side mosfet will not be allowed to turn on. when using an external sense resistor r sense is the resistance of the sense resistor. vout vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 c5 56p 0402 0402 0402 r3 20k0 r5 14k3
11 ? 2007 semtech corp. www.semtech.com SC411 power management application information (cont.) the current limit circuitry also protects against negative over-current (i.e. when the current is owing from the load to pgnd through the inductor and bottom mosfet). in this case, when the bottom mosfet is turned on, the phase node, lx, will be higher than pgnd initially. the SC411 monitors the voltage at lx, and if it is greater than a set threshold voltage of 125mv (nom) the bottom mos- fet is turned off. the device then waits for approximately 2.5 s and then dl goes high for 300ns (typ) once more to sense the current. this repeats until either the over- current condition goes away or the part latches off due to output over-voltage (see output over-voltage protection). power good output the power good output is an open-drain output and re- quires a pull-up resistor. when the output voltage is 16% above or 10% below its set voltage, pgd gets pulled low. it is held low until the output voltage returns to within these tolerances once more. pgd is also held low during start- up and will not be allowed to transition high until soft start is over (440 switching cycles) and the output reaches 90% of its set voltage. there is a 5 s delay built into the pgd circuitry to prevent false transitions. output over-voltage protection when the output exceeds 16% of the its set voltage the low-side mosfet is latched on. it stays latched on and the controller is latched off until reset*. there is a 5 s delay built into the ov protection circuit to prevent false transitions. output under-voltage protection when the output is 30% below its set voltage the output is latched in a tri-stated condition. it stays latched and the controller is latched off until reset*. there is a 5 s delay built into the uv protection circuit to prevent false transitions. por, uvlo and soft-start an internal power-on reset (por) occurs when vcca ex- ceeds 3v, starting up the internal biasing. vcca under- voltage lockout (uvlo) circuitry inhibits the controller until vcca rises above 4.2v. at this time the uvlo circuitry resets the fault latch and soft-start counter, and allows switching to occur if the device is enabled. switching al- ways starts with dl to charge up the bst capacitor. with the soft-start circuit (automatically) enabled, it will pro- gressively limit the output current (by limiting the current out of the ilim pin) over a predetermined time period of 440 switching cycles. the ramp occurs in four steps: 1) 110 cycles at 25% ilim with double minimum off-time (for purposes of the on-time one-shot, there is an internal positive offset of 120mv to vout during this period to aid in startup). 2) 110 cycles at 50% ilim with normal minimum off- time. 3) 110 cycles at 75% ilim with normal minimum off-time. 4) 110 cycles at 100% ilim with normal minimum off- time. at this point the output under-voltage and power good cir- cuitry is enabled. there is 100mv of hysteresis built into the uvlo circuit and when vcca falls to 4.1v (nom) the output drivers are shut down and tri-stated. mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side, and larger low-side power mosfets. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on until dl is fully off (below ~1v). semtech?s smartdriver tm fet drive rst pulls dh high with a pull-up resistance of 10 (typ) until lx = 1.5v (typ). at this point, an additional pull-up device is activated, reducing the resistance to 2 (typ); this negates the need for an external gate or boost re- sistor. the adaptive dead time circuit also monitors the phase node, lx, to determine the state of the high side mosfet, and prevents the low side mosfet from turning on until dh is fully off (lx below ~1v). be sure there is low resistance and low inductance between the dh and dl outputs to the gate of each mosfet. * note: to reset from any fault, vcca or en/psv must be toggled.
12 ? 2007 semtech corp. www.semtech.com SC411 power management dropout performance the output voltage adjust range for continuous-conduction operation is limited by the xed 550ns (maximum) mini- mum off-time one-shot. for best dropout performance, use the slowest on-time setting of 200khz. when work- ing with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the ic duty-factor limitation is given by: be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case dropout duty-factor calculations. SC411 system dc accuracy two ic parameters affect system dc accuracy, the error comparator threshold voltage variation and the switching frequency variation with line and load. the error com- parator threshold does not drift signi cantly with supply and temperature. thus, the error comparator contributes 1.2% or less to dc system inaccuracy. board components and layout also in uence dc accuracy. the use of 1% feedback resistors contribute 1%. if tighter dc accuracy is required use 0.1% feedback resistors. the on-pulse in the SC411 is calculated to give a pseu- do- xed frequency. nevertheless, some frequency varia- tion with line and load can be expected. this variation changes the output ripple voltage. because constant-on regulators regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the feedback resistors are chosen to divide down the output by a factor of ve, the valley of the output ripple will be vout. for example: if vout is 2.5v and the ripple is 50mv with vbat = 6v, then the measured dc output will be 2.525v. if the ripple increases to 80mv with vbat = 25v, then the measured dc output will be 2.540v. the output inductor value may change with current. this will change the output ripple and thus the dc output volt- age but it will not change the frequency. ) ma x ( off t ) mi n ( on t ) mi n ( on t duty + = switching frequency variation with load can be minimized by choosing mosfets with lower rds(on). high rds(on) mosfets will cause the switching frequency to increase as the load current increases. this will reduce the ripple and thus the dc output voltage. design procedure prior to designing an output and making component selec- tions, it is necessary to determine the input voltage range and the output voltage speci cations. for purposes of demonstrating the procedure the output for the schemat- ic in figure 4 on page 17 will be designed. the maximum input voltage (v bat(max) ) is determined by the highest ac adaptor voltage. the minimum input voltage (v bat(min) ) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. for the purposes of this design example we will use a v bat range of 8v to 20v. four parameters are needed for the output: 1) nominal output voltage, v out (we will use 1.2v). 2) static (or dc) tolerance, tol st (we will use +/-4%). 3) transient tolerance, tol tr and size of transient (we will use +/-8% and 6a for purposes of this demonstration). 4) maximum output current, i out (we will design for 6a). switching frequency determines the trade-off between size and ef ciency. increased frequency increases the switching losses in the mosfets, since losses are a func- tion of vin 2 . knowing the maximum input voltage and budget for mosfet switches usually dictates where the design ends up. a default r ton value of 1m is suggested as a starting point, but this is not set in stone. the rst thing to do is to calculate the on-time, t on , at v bat(min) and v bat(max) , since this depends only upon v bat , v out and r ton . for vout < 3.3v: application information (cont.) t on_vbat(min) = 3.3 10 -12 rt on + 37 10 3 v out v bat(min) + 50 10 -9 s
13 ? 2007 semtech corp. www.semtech.com SC411 power management application information (cont.) and, from these values of ton we can calculate the nominal switching frequency as follows: and, t on is generated by a one-shot comparator that samples v bat via r ton , converting this to a current. this current is used to charge an internal 3.3pf capacitor to v out . the equations above re ect this along with any internal com- ponents or delays that in uence t on . for our example we select r ton = 1m : t on_vbat(min) = 563ns and t on_vbat(max) = 255ns fsw_vbat(min) = 266khz and f sw_vbat(max) = 235khz now that we know t on we can calculate suitable values for the inductor. to do this we select an acceptable inductor ripple current. the calculations below assume 50% of i out which will give us a starting place. and, for our example: l vbat(min) = 1.3 h and l vbat(max) = 1.6 h we will select an inductor value of 2.2 h to reduce the ripple current, which can be calculated as follows: () hz t v v f ) mi n ( vbat _ on ) mi n ( bat out ) mi n ( vbat _ sw ? = () hz t v v f ) ma x ( vbat _ on ) ma x ( bat out ) ma x ( vbat _ sw ? = and, for our example: i ripple_vbat(min) = 1.74a p-p and i ripple_vbat(max) = 2.18a p-p from this we can calculate the minimum inductor current rating for normal operation: for our example: i inductor(min) = 7.1a (min) next we will calculate the maximum output capacitor equivalent series resistance (esr). this is determined by calculating the remaining static and transient tolerance allowances. then the maximum esr is the smaller of the calculated static esr (r esr_st(max) ) and transient esr (r esr_tr(max) ): where err st is the static output tolerance and err dc is the dc error. the dc error will be 1.2% plus the tolerance of the feedback resistors, thus 2.2% total for 1% feedback resistors. for our example: err st = 48mv and err dc = 26.4mv, therefore, r esr_st(max) = 19.8m where err tr is the transient output tolerance. note that this calculation assumes that the worst case load tran- sient is full load. for half of full load, divide the i out term by 2. ) mi n ( ) ma x ( vbat _ ripple ) ma x ( out ) mi n ( induct or a 2 i i i + = () ohm s i 2 err err r ) ma x ( vbat _ ripple dc st ) ma x ( st _ esr ? ? = () ohm s 2 i i err err r ) ma x ( vbat _ ripple out dc tr ) ma x ( tr _ esr ? ? ? ? ? ? ? ? + ? = t on_vbat(max) = 3.3 10 -12 rt on + 37 10 3 v out v bat(max) + 50 10 -9 s l vbat(min) = v bat(min) v out t on_vbat(min) 0.5 i out h l vbat(max) = v bat(max) v out t on_vbat(max) 0.5 i out h t on_vbat(min) a p-p i ripple_vbat(min) = v bat(min) v out l a p-p l i ripple_vbat(max) = v bat(max) v out t on_vbat(max)
14 ? 2007 semtech corp. www.semtech.com SC411 power management application information (cont.) for our example: err tr = 96mv and err dc = 26.4mv, therefore, r esr_tr(max) = 9.8m for a full 6a load transient we will select a value of 12.5m maximum for our de- sign, which would be achieved by using two 25m output capacitors in parallel. note that for constant-on converters there is a minimum esr requirement for stability which can be calculated as follows: this criteria should be checked once the output capacitance has been determined. now that we know the output esr we can calculate the output ripple voltage: and, for our example: v ripple_vbat(max) = 27mv p-p and v ripple_vbat(min) = 22mv p-p note that in order for the device to regulate in a controlled manner, the ripple content at the feedback pin, v fb , should be approximately 15mv p-p at minimum v bat , and worst case no smaller than 10mv p-p . if v ripple_vbat(min) is less than 15mv p-p the above component values should be revisited in order to improve this. quite often a small capacitor, c top , is required in parallel with the top feedback resis- tor, r top , in order to ensure that v fb is large enough. c top should not be greater than 100pf. the value of c top can be calculated as follows, where r bot is the bottom feed- back resistor. sw out ) mi n ( esr f c 2 3 r ? ? ? = firstly calculating the value of z top required: () ohms 015 . 0 v 015 . 0 r z ) mi n ( vbat _ ripple bot top ? ? = secondly calculating the value of c top required to achieve this: for our example we will use r top = 20.0k and r bot = 14.3k , therefore, z top = 6.67k and c top = 60pf we will select a value of c top = 56pf. calculating the value of vfb based upon the selected c top : p p top ) mi n ( vbat _ sw top bot bot ) mi n ( vbat _ ripple ) mi n ( vbat _ fb v c f 2 r 1 1 r r v v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? = for our example: v fb_vbat(min) = 14.8mv p-p - good next we need to calculate the minimum output capaci- tance required to ensure that the output voltage does not exceed the transient maximum limit, poslim tr , starting from the actual static maximum, v out_st_pos , when a load release occurs: for our example: v out_st_pos = 1.226v p p ) ma x ( vbat _ ripple esr ) ma x ( vbat _ ripple v i r v ? ? = p p ) mi n ( vbat _ ripple esr ) mi n ( vbat _ ripple v i r v ? ? = f f 2 r 1 z 1 c ) mi n ( vbat _ sw top top top ? ? ? ? ? ? ? ? ? ? ? = v err v v dc out pos _ st _ out + = v tol v poslim tr out tr ? =
15 ? 2007 semtech corp. www.semtech.com SC411 power management where tol tr is the transient tolerance. for our example: poslim tr = 1.296v the minimum output capacitance is calculated as follows: this calculation assumes the absolute worst case condi- tion of a full-load to no load step transient occurring when the inductor current is at its highest. the capacitance required for smaller transient steps may be calculated by substituting the desired current for the i out term. for our example: c out(min) = 626 f. we will select 440 f, using two 220 f, 25m capacitors in parallel. for smaller load release overshoot, 660 f may be used. alternatively, one 15m or 12m , 220 f, 330 f or 470 f capacitor may be used (with the appro- priate change to the calculation for c top ), depending upon the load transient requirements. next we calculate the rms input ripple current, which is largest at the minimum battery voltage: () rms mi n _ bat out out ) mi n ( bat out ) rms ( in a v i v v v i ? ? ? = for our example: i in(rms) = 2.14a rms input capacitors should be selected with suf cient ripple current rating for this rms current, for example a 10 f, 1210 size, 25v ceramic capacitor can handle approxi- mately 3a rms . refer to manufacturer?s data sheets and derate appropriately. finally, we calculate the current limit resistor value. as described in the current limit section, the current limit looks at the ?valley current?, which is the average output current minus half the ripple current. we use the maxi- mum room temperature speci cation for mosfet r ds(on) at v gs = 4.5v for purposes of this calculation: the ripple at low battery voltage is used because we want to make sure that current limit does not occur under nor- mal operating conditions. for our example: i valley = 5.13a, r ds(on) = 9m and r ilim = 7.76k we select the next lowest 1% resistor value: 7.68k thermal considerations the junction temperature of the device may be calculated as follows: where: t a = ambient temperature (c) p d = power dissipation in (w) ja = thermal impedance junction to ambient from absolute maximum ratings (c/w) the power dissipation may be calculated as follows: where: vcca = chip supply voltage (v) i vcca = operating current (a) vddp = gate drive supply voltage (v) application information (cont.) c cout(min) = l f i ripple_vbat(max) i out + 2 poslim tr 2 v out_st_pos 2 2 a 2 i i i ) mi n ( vbat _ ripple out valley ? = () ohm s 10 10 4 . 1 r 2 . 1 i r 6 ) on ( ds valley ilim ? ? ? ? ? = c p t t ja d a j ? + = w d ma 1 vbst f q v i vddp i vcca p g g vddp vcca d ? ? + ? ? + ? + ? =
16 ? 2007 semtech corp. www.semtech.com SC411 power management application information (cont.) i vddp = gate drive operating current (a) v g = gate drive voltage, typically 5v (v) q g = fet gate charge, from the fet datasheet (c) f = switching frequency (khz) vbst = boost pin voltage during t on (v) d = duty cycle inserting the following values for vbat (min) condition (since this is the worst case condition for power dissipation in the controller) as an example (vout = 1.2v), t a = 85c ja = 100c/w vcca = vddp = 5v i vcca = 1100 a (data sheet maximum) i vddp = 150 a (data sheet maximum) v g = 5v q g = 60nc f = 266khz vbat (min) = 8v vbst (min) = vbat (min) +vddp = 13v d (min) = 1.2/8 = 0.15 gives us, w 088 . 0 15 . 0 10 1 13 10 266 10 60 5 10 150 5 10 1100 5 p 3 3 9 6 6 d = ? ? ? + ? ? ? ? + ? ? + ? ? = ? ? ? ? and, c 8 . 93 100 088 . 0 85 t j = ? + = as can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special thermal consideration during layout. the reference design is shown in figure on page 17. an additional design optimized for ef ciency and capable of a higher load current of 10a is shown in figure 11 on page 21.
17 ? 2007 semtech corp. www.semtech.com SC411 power management layout guidelines figure 4: reference design one (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and maximize heat dissipation. the ic ground reference, vssa, and the power ground pin, pgnd, should both connect directly to the device thermal pad. the thermal pad should connect to the ground plane(s) using multiple vias. the vout feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate drives. route the feedback trace in a quiet layer (if possible) from the output capacitor back to the chip. all compo- nents should be located adjacent to their respective pins with an emphasis on the chip decoupling capacitors (vcca and vddp) and the components that are shown connecting to vssa in the above schematic. make any ground con- nections simply to the ground plane. power sections should connect directly to the ground plane(s) using multiple vias as required for current handling (in- cluding the chip power ground connections). power components should be placed to minimize loops and reduce loss- es. make all the connections on one side of the pcb using wide copper lled areas if possible. do not use ?minimum? land patterns for power components. minimize trace lengths between the gate drivers and the gates of the mosfets to reduce parasitic impedances (and mosfet switching losses), the low-side mosfet is most critical. maintain a length to width ratio of <20:1 for gate drive signals. use multiple vias as required by current handling requirements (and to reduce parasitics) if routed on more than one layer. current sense connections must always be made using kelvin connections to ensure an accurate signal, with the current limit resistor located at the device. we will examine the reference design used in the design procedure section while explaining the layout guidelines in more detail. vout c8 1nf vbat r1 1m pgood q1 irf7811av c10 1uf r4 7k87 c1 0u1 d1 c2 2n2/50v vbat 5vsus l1 2u2 + c6 220u/25m vout r2 10r 5vsus vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 q2 fds6676s c5 56p 0402 0402 0402 0402 0402 0402 0603 0603 0402 0603 sod323 0402 c3 0u1/25v 0603 c4 10u/25v 1210 + c7 220u/25m vbat = 8v to 20v vout = 1.2v @ 6a 7343 7343 c9 1uf r3 20k0 r5 14k3
18 ? 2007 semtech corp. www.semtech.com SC411 power management the layout can be considered in two parts, the control section referenced to vssa and the power section. looking at the control section rst, locate all components referenced to vssa on the schematic and place these components at the chip. drop vias to the ground plane as needed. figure 5: components connected to vssa figure 6: control section example in figure 6 above, all components referenced to vssa have been placed and connected to the ground plane with vias. decoupling capacitors c9 and c10 are as close as possible to their pins and connected to the ground plane with vias. note how the vssa and pgnd pins are connected directly to the thermal pad, which has 4 vias to the ground plane (not shown). vout vbat c8 1nf r1 1m c10 1uf 5vsus r2 10r 5vsus vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 c5 56p 0402 0402 0402 0402 0402 0402 0603 0603 c9 1uf r3 20k0 r5 14k3
19 ? 2007 semtech corp. www.semtech.com SC411 power management as shown below, vout should be routed away from noisy traces (such as bst, dh, dl and lx) and in a quiet layer (if possible) to the output capacitor(s). figure 7: vout sense trace routing next, the schematic in figure 8 below shows the power section. the highest di/dts occur in the input loop (highlight- ed in red) and thus this loop should be kept as small as possible. figure 8: power section and input loop the input capacitors should be placed with the highest frequency capacitors closest to the loop to reduce emi. use large copper pours to minimize losses and parasitics. see figure 9 for an example. vout + c6 220u/25m vout vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 c5 56p 0402 0402 0402 + c7 220u/25m 7343 7343 r3 20k0 r5 14k3 q1 ir f7811av c2 2n2/50v vbat l1 2u2 + c6 220u/25m vout q2 fd s6676s c3 0u1/25v 0402 0603 c4 10u/25v 1210 + c7 220u/25m 7343 7343
20 ? 2007 semtech corp. www.semtech.com SC411 power management figure 9: power component placement and copper pours key points for the power section: 1) there should be a very small input loop, well decoupled. 2) the phase node should be a large copper pour, but compact since this is the noisiest node. 3) input power ground and output power ground should not connect directly, but through the ground planes instead. 4) the current limit resistor should be placed as close as possible to the ilim and lx pins. connecting the control and power sections should be accomplished as follows (see figure 10 on the following page): 1) route vout in a ?quiet? layer away from noise sources. 2) route dl, dh and lx (low side fet gate drive, high side fet gate drive and phase node) to chip using wide traces with multiple vias if using more than one layer. these connections to be as short as possible for loop minimization, with a length to width ratio less than 20:1 to minimize impedance. dl is the most critical gate drive, with power ground as its return path. lx is the noisiest node in the circuit, switching between vbat and ground at high frequencies, thus should be kept as short as practical. dh has lx as its return path. 3) bst is also a noisy node and should be kept as short as possible. 4) connect pgnd and vssa directly to the thermal pad, and connect the thermal pad to the ground plane using mul- tiple vias.
21 ? 2007 semtech corp. www.semtech.com SC411 power management figure 10: connecting the control and power sections q1 irf7811av r4 7k87 l1 2u2 vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 q2 fds6676s 0402 phase nodes (black) to be copper islands (preferred) or wide copper traces. gate drive traces (red) and phase node traces (blue) to be wide copper traces (l:w < 20:1) and as short as possible, with dl the most critical. vout vbat pgood 5vsus vbat vout 5vsus 0402 0402 0402 0402 0402 0402 0603 0603 0402 0603 sod323 0402 0603 1210 7343 7343 l1 = 1.5uh vishay ihlp 5050ce vbat = 8v to 20v vout = 1.2v @ 10a c6, c7 = 470uf / 15milli ohm sanyo pos cap 2r5tpe470mf d1 d1 + c6 470u/15m + c6 470u/15m c5 220p c5 220p r1 806k r1 806k q2 irf7832 q2 irf7832 c9 1uf c9 1uf r5 20k r5 20k r3 28k r3 28k c4 10u/25v c4 10u/25v + c7 470u/15m + c7 470u/15m vout 1 vcca 2 fb 3 pgd 4 nc 5 vssa 6 pgnd 7 dl 8 vddp 9 ilim 10 lx 11 dh 12 bst 13 nc 14 en/psv 15 ton 16 tpad u1 SC411 u1 SC411 r2 10r r2 10r r4 7k15 r4 7k15 c3 0u1/25v c3 0u1/25v c8 1nf c8 1nf c10 1uf c10 1uf c1 0u1 c1 0u1 c2 2n2/50v c2 2n2/50v l1 1u5 l1 1u5 q1 irf7821 q1 irf7821 figure 11: high ef ciency design
22 ? 2007 semtech corp. www.semtech.com SC411 power management 1.2v ef ciency (power save mode) (high ef ciency design, page 21) typical characteristics 1.2v output voltage (power save mode) vs. output current vs. input voltage 1.2v switching frequency (power save mode) vs. output current vs. input voltage 1.2v ef ciency (continuous conduction mode) (high ef ciency design, page 21) 1.2v output voltage (continuous conduction mode) vs. output current vs. input voltage 1.2v switching frequency (continuous conduction mode) vs. output current vs. input voltage 1.180 1.184 1.188 1.192 1.196 1.200 1.204 1.208 1.212 1.216 1.220 0123456 i out (a) v out (v) v bat = 20v v bat = 8v 1.180 1.184 1.188 1.192 1.196 1.200 1.204 1.208 1.212 1.216 1.220 0123456 i out (a) v out (v) v bat = 20v v bat = 8v 0 50 100 150 200 250 300 350 400 0123456 i out (a) frequency (khz) v bat = 20v v bat = 8v 0 50 100 150 200 250 300 350 400 0123456 i out (a) frequency (khz) v bat = 20v v bat = 8v 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) v bat = 20v v bat = 8v 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) v bat = 8v v bat = 20v for ef ciency charts, refer to high ef ciency design, figure 11 on page 21. for all other data, refer to the reference design, figure 4 on page 17.
23 ? 2007 semtech corp. www.semtech.com SC411 power management typical characteristics load transient response, continuous conduction mode, 0a to 6a to 0a trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 20v/div trace 3: not connected trace 4: load current, 5a/div timebase: 40 s/div. load transient response, continuous conduction mode, 0a to 6a zoomed trace 1: 1.2v, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10 s/div. load transient response, continuous conduction mode, 6a to 0a zoomed trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10 s/div. please refer to figure 4 on page 17 for test schematic
24 ? 2007 semtech corp. www.semtech.com SC411 power management typical characteristics load transient response, power save mode, 0a to 6a to 0a trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 20v/div trace 3: not connected trace 4: load current, 5a/div timebase: 40 s/div. startup (ccm), en/psv 0v to floating trace 1: 1.2v, 20mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10 s/div. load transient response, power save mode, 6a to 0a zoomed trace 1: 1.2v, 50mv/div., ac coupled trace 2: lx, 10v/div trace 3: not connected trace 4: load current, 5a/div timebase: 10 s/div. please refer to figure 4 on page 17 for test schematic
25 ? 2007 semtech corp. www.semtech.com SC411 power management typical characteristics startup (psv), en/psv going high trace 1: 1.2v, 0.5v/div. trace 2: lx, 10v/div trace 3: en/psv, 5v/div trace 4: pgd, 5v/div. timebase: 1ms/div. startup (ccm), en/psv 0v to floating trace 1: 1.2v, 0.5v/div. trace 2: lx, 10v/div trace 3: en/psv, 5v/div trace 4: pgd, 5v/div. timebase: 1ms/div. please refer to figure 4 on page 17 for test schematic
26 ? 2007 semtech corp. www.semtech.com SC411 power management indicator (laser mark) pin 1 dimensions nom inches n bbb aaa a2 a1 e1 d1 dim l e e d a b min max millimeters min max nom .153 .157 .161 3.90 4.00 4.10 .153 .157 .161 3.90 4.00 4.10 e1 .003 .010 .079 16 .012 .085 - .000 .031 (.008) 0.08 0.30 16 .014 .089 0.25 2.00 .040 - .002 - 0.00 0.80 2.25 0.35 2.15 - 0.05 1.00 (0.20) .004 0.10 2.00 2.15 2.25 0.65 bsc .026 bsc 0.30 .012 .020 .016 0.40 0.50 .089 .085 .079 d/2 2 a a1 1 lxn bbb c a b a2 bxn e seating plane c e/2 d1 n e/2 aaa c controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. 1. 2. notes: ad e b - - - - marking information outline drawing - mlpq-16 top marking SC411 yyww xxxxx xxxxx yyww = date code (example: 0552) xxxxx = semtech lot number (example: e9010) xxxxx = (example: 1-100)
27 ? 2007 semtech corp. www.semtech.com SC411 power management land pattern - mlpq-16 this land patter n is for referenc e purposes only. consult your manufacturin g group to ensure your company's manufacturin g guidelines are met. notes: 1. 2x g h 2x (c) 2x z x p y k c z p y x g k h .189 .026 .016 .037 .114 .091 .091 4.80 0.40 0.95 0.65 2.30 2.30 2.90 dim (3.85) millimeters dimensions (.152) inches semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 contact information

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